Area-Efficient Full Adder Architectures: Exploring Compact Full Adder Designs Using SRL and GDI

EasyChair Preprint 14901

Abstract

Area-efficient full-adder architectures are crucial for modern digital circuits, particularly in space-constrained applications such as portable devices and low-power systems. This paper explores two promising approaches for compact full adder designs: Shift Register Logic (SRL) and Gate Diffusion Input (GDI). Both techniques aim to reduce transistor count, power consumption, and circuit complexity while maintaining high performance.

The SRL-based full adder leverages the inherent compactness of shift registers, minimizing area by reducing the number of logic gates required for sum and carry generation. Meanwhile, GDI-based full adders focus on optimizing transistor-level design by utilizing a simpler and more efficient gate structure, enabling significant reductions in power and area compared to traditional CMOS full adders.

Through a detailed analysis of both architectures, we evaluate their trade-offs in terms of area efficiency, power consumption, and delay. Additionally, we propose potential hybrid approaches that combine the advantages of SRL and GDI, paving the way for even more compact and efficient full adder designs. The results demonstrate that both SRL and GDI offer significant improvements over conventional designs, making them viable candidates for use in future low-power and high-performance VLSI systems.

Keyphrases: Digital Circuit Design, area efficiency, power consumption, propagation delay

@booklet{EasyChair:14901,
  author    = {Ayuns Luz and Harold Jonathan},
  title     = {Area-Efficient Full Adder Architectures: Exploring Compact Full Adder Designs Using SRL and GDI},
  howpublished = {EasyChair Preprint 14901},
  year      = {EasyChair, 2024}}