Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic

EasyChair Preprint 13769

Abstract

Memristive memory (memristor) enables logic operations within the memory array, where memristors in the same row or column serve as a logic gate. Logic functions are implemented in the memory through netlist synthesis and in-memory mapping, which assigns each gate operation to specific memristors. The goal is to minimize latency, which represents the number of clock cycles required to complete the operations. While multiple gate operations can be executed in the same clock cycle, additional cycles may be needed for copy operations to align the gate operations. Therefore, assigning each operation to a clock cycle is a challenge. Furthermore, the results of in-memory mapping vary depending on the input netlist. To further reduce latency, an integrated approach is necessary to provide an optimal netlist. We propose two approaches: (1) graph coloring-based in-memory mapping, where the gates are colored to assign sets of gates that operate simultaneously, and (2) integration with mapping-aware netlist synthesis, which iteratively revises the input netlist based on latency evaluation; an incremental method is employed to accelerate the process. Experiments demonstrate that the coloring-based in-memory mapping reduces latency by 17% compared to the state-of-the-art method. The integrated approach achieves an additional 15% reduction in latency.

Keyphrases: In-memory mapping, Memristor-aided logic, graph coloring, logic synthesis

@booklet{EasyChair:13769,
  author    = {Seunggyu Lee and Wonjae Lee and Youngsoo Shin},
  title     = {Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic},
  howpublished = {EasyChair Preprint 13769},
  year      = {EasyChair, 2024}}